? semiconductor components industries, llc, 2010 october, 2010 ? rev. 7 1 publication order number: mcr8dsm/d mcr8dsm, mcr8dsn preferred device sensitive gate silicon controlled rectifiers reverse blocking thyristors designed for high volume, low cost, industrial and consumer applications such as motor control; process control; temperature, light and speed control. features ? small size ? passivated die for reliability and uniformity ? low level triggering and holding characteristics ? available in two package styles surface mount lead form ? case 369c miniature plastic package ? straight leads ? case 369 ? epoxy meets ul 94 v ? 0 @ 0.125 in ? esd ratings: human body model, 3b 8000 v machine model, c 400 v ? pb ? free packages are available maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit peak repetitive off ? state voltage (note 1) (t j = ? 40 to 110 c, sine wave, 50 hz to 60 hz) mcr8dsm mcr8dsn v drm, v rrm 600 800 v on ? state rms current (180 conduction angles; t c = 90 c) i t(rms) 8.0 a average on ? state current (180 conduction angles; t c = 90 c) i t(av) 5.1 a peak non-repetitive surge current (1/2 cycle, sine wave 60 hz, t j = 110 c) i tsm 90 a circuit fusing consideration (t = 8.3 msec) i 2 t 34 a 2 sec forward peak gate power (pulse width 10 sec, t c = 90 c) p gm 5.0 w forward average gate power (t = 8.3 msec, t c = 90 c) p g(av) 0.5 w forward peak gate current (pulse width 10 sec, t c = 90 c) i gm 2.0 a operating junction temperature range t j ? 40 to 110 c storage temperature range t stg ? 40 to 150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. v drm and v rrm for all types can be applied on a continuous basis. ratings apply for negative gate voltage; positive gate voltage shall not be applied concurrent with negative potential on the anode. blocking voltages shall not be tested with a constant current source such that the voltage ratings of the device are exceeded. scrs 8 amperes rms 600 ? 800 volts preferred devices are recommended choices for future use and best overall value. k g a pin assignment 1 2 3 anode gate cathode 4 anode dpak case 369c style 4 marking diagram y = year ww = work week cr8dsx = device code x= m or n g=pb ? free package yww cr 8dsxg see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information http://onsemi.com 1 2 3 4
mcr8dsm, mcr8dsn http://onsemi.com 2 thermal characteristics characteristic symbol max unit thermal resistance ? junction ? to ? case ? junction ? to ? ambient ? junction ? to ? ambient (note 2) r jc r ja r ja 2.2 88 80 c/w maximum lead temperature for soldering purposes 1/8 from case for 10 seconds t l 260 c electrical characteristics (t j = 25 c unless otherwise noted) characteristics symbol min typ max unit off characteristics peak repetitive forward or reverse blocking current (v ak = rated v drm or v rrm ; r gk = 1.0 k ) (note 3) t j = 25 c t j = 110 c i drm i rrm ? ? ? ? 10 500 a on characteristics peak reverse gate blocking voltage (i gr = 10 a) v grm 10 12.5 18 v peak reverse gate blocking current (v gr = 10 v) i rgm ? ? 1.2 a peak forward on ? state voltage (note 4) (i tm = 16 a) v tm ? 1.4 1.8 v gate trigger current (continuous dc) (note 5) (v d = 12 v, r l = 100 )t j = 25 c t j = ? 40 c i gt 5.0 ? 12 ? 200 300 a gate trigger voltage (continuous dc) (note 5) (v d = 12 v, r l = 100 )t j = 25 c t j = ? 40 c t j = 110 c v gt 0.45 ? 0.2 0.65 ? ? 1.0 1.5 ? v holding current (v d = 12 v, initiating current = 200 ma, r gk = 1 k )t j = 25 c t j = ? 40 c i h 0.5 ? 1.0 ? 6.0 10 ma latching current (v d = 12 v, i g = 2.0 ma, r gk = 1 k )t j = 25 c t j = ? 40 c i l 0.5 ? 1.0 ? 6.0 10 ma total turn ? on time (source voltage = 12 v, r s = 6.0 k , i t = 16 a(pk), r gk = 1.0 k ) (v d = rated v drm , rise time = 20 ns, pulse width = 10 s) tgt ? 2.0 5.0 s dynamic characteristics critical rate of rise of off ? state voltage (v d = 0.67 x rated v drm , exponential waveform, r gk = 1.0 k , t j = 110 c) dv/dt 2.0 10 ? v/ s 2. surface mounted on minimum recommended pad size. 3. ratings apply for negative gate voltage or r gk = 1.0 k . devices shall not have a positive gate voltage concurrently with a negative voltage on the anode. devices should not be tested with a constant current source for forward and reverse blocking capability such that the voltage applied exceeds the rated blocking voltage. 4. pulse test; pulse width 2.0 msec, duty cycle 2%. 5. r gk current not included in measurements. ordering information device package shipping ? mcr8dsmt4 dpak 2500 / tape & reel mcr8dsmt4g dpak (pb ? free) MCR8DSNT4 dpak MCR8DSNT4g dpak (pb ? free) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mcr8dsm, mcr8dsn http://onsemi.com 3 + current + voltage v tm i drm at v drm i h symbol parameter v drm peak repetitive off ? state forward voltage i drm peak forward blocking current v rrm peak repetitive off ? state reverse voltage i rrm peak reverse blocking current v tm peak on ? state voltage i h holding current voltage current characteristic of scr anode + on state reverse blocking region (off state) reverse avalanche region anode ? forward blocking region i rrm at v rrm (off state) figure 1. average current derating figure 2. on ? state power dissipation 6.0 0 i t(av) , average on-state current (amps) 110 105 100 i t(av) , average on-state current (amps) 3.0 6.0 0 8.0 4.0 2.0 0 t c , maximum allowable case temperature ( c) p 95 85 1.0 2.0 3.0 1.0 2.0 6.0 10 12 , average power dissipation (watts) (av) dc 180 120 90 60 = 30 dc 180 120 90 60 = 30 5.0 4.0 5.0 90 4.0 = conduction angle = conduction angle
mcr8dsm, mcr8dsn http://onsemi.com 4 figure 3. on ? state characteristics figure 4. transient thermal response figure 5. typical gate trigger current versus junction temperature figure 6. typical gate trigger voltage versus junction temperature 5.0 0 v t , instantaneous on-state voltage (volts) 100 10 1.0 0.1 t, time (ms) 1.0 0.1 1.0 0.1 0.01 4.0 -25 20 -40 t j , junction temperature ( c) 1000 10 t j , junction temperature ( c) -25 65 -40 0.1 20 5.0 i r (t) , transient thermal resistance 1.0 3.0 10 100 1000 10 k , gate trigger current ( a) i gt 50 110 65 5.0 110 35 50 v gt , gate trigger voltage (volts) , instantaneous on-state current (amps) t 80 typical @ t j = 25 c maximum @ t j = 25 c maximum @ t j = 110 c z jc(t) = r jc(t) r(t) 1.0 1.0 2.0 -10 35 95 100 -10 95 80 (normalized) gate open r gk = 1.0 k figure 7. typical holding current versus junction temperature figure 8. typical latching current versus junction temperature 65 110 -40 t j , junction temperature ( c) t j , junction temperature ( c) i h , holding current (ma) i 1.0 0.1 -25 5.0 20 50 95 , latching current (ma) l 10 -10 35 80 r gk = 1.0 k 65 110 -40 1.0 0.1 -25 5.0 20 50 95 10 -10 35 80 r gk = 1.0 k
mcr8dsm, mcr8dsn http://onsemi.com 5 figure 9. holding current versus gate ? cathode resistance 1000 10 k 100 r gk , gate-cathode resistance (ohms) 10 6.0 4.0 2.0 0 i t j = 25 c figure 10. exponential static dv/dt versus gate ? cathode resistance and junction temperature 100 r gk , gate-cathode resistance (ohms) 1000 10 1.0 static dv/dt (v/ s) t j = 110 c 1000 i gt = 10 a figure 11. exponential static dv/dt versus gate ? cathode resistance and peak voltage static dv/dt (v/ s) figure 12. exponential static dv/dt versus gate ? cathode resistance and gate trigger current sensitivity 8.0 i gt = 25 a , holding current (ma) h 100 90 c 70 c 100 r gk , gate-cathode resistance (ohms) 1000 10 1.0 t j = 110 c 1000 100 v pk = 800 v 600 v 400 v 100 r gk , gate-cathode resistance (ohms) 1000 10 1.0 v d = 800 v t j = 110 c 1000 100 i gt = 10 a static dv/dt (v/ s) i gt = 25 a
mcr8dsm, mcr8dsn http://onsemi.com 6 package dimensions dpak (single gauge) case 369c ? 01 issue d b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw style 4: pin 1. cathode 2. anode 3. gate 4. anode on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mcr8dsm/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
|
